MEP

MEP stands for Mechanical, Electrical and Plumbing. Ibis Academy offers state of the art facilities and faculties for the six months short term course in MEP design that will groom a candidate to the level of a perfect MEP design engineer. We have high configuration computers installed at our MEP design lab which helps our students to work in a real-life scenario comfortably. MEP engineers are sought very much across the globe since the approval for any construction is purely based on the design provided by MEP engineers. Our students are allowed to work under real-life on-going MEP projects in GCC countries, Singapore, Malaysia etc for a period of 6 months. The MEP program Certificate of Completion we provide hence is equivalent to the 6 months work experience.

10

Campuses across India

135+

Recruiters

8+

Awards

4

Lacs / Annum – Avg. Package

5500+

Alumni

200+

Faculty With Industry Experience


    Enroll for Scholarship !
    worth Rs.25000



    Requirements

    The undergraduates, graduates, or postgraduates from below streams can take up the VLSI course and make a career in VLSI Industry. BE/BTech in EEE/ECE or ME/MTech/MS in Electronics.

    Also, the eligibility criteria for securing admission for this VLSI course are 60% & more throughout your academics

    Opportunity

    The industry offers a variety of roles in the semiconductor industry including

    RTL Design Engineer

    SoC Design Engineer

    Digital Design Engineer

    SoC
    Verification Engineer

    AMS
    Verification Engineer

    Application
    Engineer

    ASIC
    Verification Engineer

    FAQs

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    Admission

    Career Opportunities

    Course Delivery

    Curriculum

    Digital Electronics

    Learners are able to describe Digital Number System, Logic Gates, Logic Circuits, Counters, Shift Registers, FIFOs, Memories, Arbiters, etc. 

    Verilog

    Learners are able to describe Data Types of Verilog, Operators, Types of Assignments, Timing Control Statements, Branching and Iterative, statements, Tasks and Functions, Design various logic circuits using all type of modelling. 

    UVM – Universal Verification Methodology 

    Learners area ble to describe How to build reusable Test, Bench Architecture, Register Modelling, and How to verify complex IPs. 

    Project 

    Learners are able to code the entire design and are able to verify it using the verification language and TB Methodologies. 

    Static Timing Analysis 

    Learners are able to describe Timing Paths, Skews, Latencies, Setup and Hold Time Calculations, and Methods to Improve Timing 

    System Verilog 

    Learners are able to describe OOPs Concepts, Constraint Random, verification, Assertion Based, Verification, Building Test Bench Architecture, and Coverage Modeling 

    Design Automation Using Python Scripting

    Learners are able to describe how they can automate manual repetitive tasks using python scripting language

    Personality Development Sessions

    Learners can communicate via email. Learners can handle interviews confidently

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